Hardware Architecture for High Radix Adaptive CORDIC algorithm. [HCORDIC]

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Hi all,

Here's my undergraduate thesis work on a variant of CORDIC algorithm


Abstract: -

CORDIC serves as an iterative algorithm to exclude the usage of hardware multipliers in estimating functions such as the sin and log. We extend upon the results of Elguibaly et al.[1], in developing a high-radix adaptive CORDIC algorithm to enhance traditional CORDIC by an average speed up of 2s. The factor s is the number of leading bits of the result mantissa that is to be approximated. We analyze the conditions for achieving the speed up; subject to simulations and FPGA implementation on Xilinx Virtex VI, to provide for a comprehensive understanding of the algorithm. The project proposes to identify a hardware architecture to implement the results of HCORDIC as a math co-processor for an existing General Purpose Computer or a DSP.
Citation:-

S. S. Oza, A. P. Shah, T. Thokala and S. David, "Pipelined implementation of high radix adaptive CORDIC as a coprocessor," 2015 International Conference on Computing and Network Communications (CoCoNet), Trivandrum, 2015, pp. 333-342.
doi: 10.1109/CoCoNet.2015.7411207
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7411207&isnumber=7411155

Source Code:-
https://github.com/ankitshah009/High-Radix-Adaptive-CORDIC

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